1. Field of the Invention
This invention relates to a semiconductor device containing a semiconductor chip and a substrate, and relates to a method of manufacturing a semiconductor device containing a semiconductor chip and a substrate.
2. Description of the Related Art
Conventionally, a semiconductor device in which a semiconductor chip is mounted on a substrate is known. Referring to FIG. 1, a semiconductor device according to the related art in which a semiconductor chip is mounted on a substrate will be described.
FIG. 1 is a cross-sectional view of a semiconductor device according to the related art in which a semiconductor chip is mounted on a substrate. As illustrated in FIG. 1, the semiconductor device 300 includes a multi-layer substrate 500, a semiconductor chip 400, solder bumps 410, and an underfill resin layer 420. A support medium 510 is formed in the central part of the multi-layer substrate 500.
A first wiring layer 610a is formed on a first principal surface 510a of the supporting medium 510. A through via 690 is formed in the supporting medium 510 to penetrate the supporting medium 510 from the first principal surface 510a to a second principal surface 510b thereof. The first wiring layer 610a is electrically connected to a fourth wiring layer 610b (which will be described later) through the through via 690. A first insulating layer 520a is formed to cover the first wiring layer 610a, and a second wiring layer 620a is formed on the first insulating layer 520a. The first wiring layer 610a and the second wiring layer 620a are electrically connected to each other through via holes 520x which penetrate the first insulating layer 520a. 
A second insulating layer 530a is formed to cover the second wiring layer 620a. A third wiring layer 630a is formed on the second insulating layer 530a. The second wiring layer 620a and the third wiring layer 630a are electrically connected to each other through via holes 530x which penetrate the second insulating layer 530a. 
A solder-resist film 550a which has an opening 550x is formed to cover the third wiring layer 630a. The portion of the third wiring layer 630a, exposed from the opening 550x of the solder-resist film 550a, serves as an electrode pad. In the following, the portion of the third wiring layer 630a exposed from opening 550x of the solder-resist film 550a will be referred to as an electrode pad 630a. In the following, the surface on which the electrode pad 630a is formed will be referred to as a first principal surface of the multi-layer substrate 500.
On the second principal surface 510b of the supporting medium 510, a fourth wiring layer 610b is formed. A third insulating layer 520b is formed to cover the fourth wiring layer 610b. A fifth wiring layer 620b is formed on the third insulating layer 520b. The fourth wiring layer 610b and the fifth wiring layer 620b are electrically connected to each other through via holes 520y which penetrate the third insulating layer 520b. 
A fourth insulating layer 530b is formed to cover the fifth wiring layer 620b. A sixth wiring layer 630b is formed on the fourth insulating layer 530b. The fifth wiring layer 620b and the sixth wiring layer 630b are electrically connected to each other through via holes 530y which penetrate the fourth insulating layer 530b. 
A solder-resist film 550b which has an opening 550y is formed to cover the sixth wiring layer 630b. The portion of the sixth wiring layer 630b, exposed from the opening 550y of the solder-resist film 550b, serves as an electrode pad. In the following, the portion of the sixth wiring layer 630b exposed from the opening 550y of the solder-resist film 550b will be referred to as an electrode pad 630b. In the following, the surface on which the electrode pad 630b is formed will be referred to as a second principal surface of the multi-layer substrate 500.
Solder bumps 680 are formed on some electrode pads 630b. When mounting the semiconductor device 300 on a circuit board (not illustrated), each solder bump 680 serves as an external connection terminal that is electrically connected to a corresponding terminal of the circuit board. Chip capacitors 100 are mounted on some electrode pads 630b. One of such electrode pads 630b and external electrodes 260a and 260b of each chip capacitor 100 are connected electrically to each other.
A semiconductor chip 400 is mounted on the first principal surface of the multi-layer substrate 500. In the semiconductor chip 400, a semiconductor integrated circuit (not illustrated) and electrode pads (not illustrated) are formed on a thinned semiconductor substrate (not illustrated) which is made of silicon or the like. The solder bumps 410 are formed on the electrode pads (not illustrated) of the semiconductor chip 400.
The electrode pads (not illustrated) of the semiconductor chip 400 are electrically connected to the corresponding electrode pads 630a of the multi-layer substrate 500 by the solder bumps 410. Examples of the material of the solder bumps 410 may include an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag and Cu. The underfill resin layer 420 is formed between the semiconductor chip 400 and the solder-resist film 550a of the multi-layer substrate 500.
Conventionally, a semiconductor device in which a semiconductor chip is built in a substrate is known. Referring to FIG. 2, a semiconductor device according to the related art in which a semiconductor chip is built in a substrate will be described.
FIG. 2 is a cross-sectional view of a semiconductor device according to the related art in which a semiconductor chip is built in a substrate. As illustrated in FIG. 2, the semiconductor device 700 includes a multi-layer substrate 800 and a semiconductor chip 450. The semiconductor chip 450 is embedded in a resin 810. A first insulating layer 820 is formed on one surface of the semiconductor chip 450 and the resin 810, and a first wiring layer 910 is formed on the first insulating layer 820. The first wiring layer 910 and electrode pads (not illustrated) of the semiconductor chip 450 are electrically connected to each other through via holes 820x which penetrate the first insulating layer 820. Namely, bumps are not used to electrically connect the semiconductor chip 450 and the multi-layer substrate 800.
A second insulating layer 830 is formed to cover the first wiring layer 910, and a second wiring layer 920 is formed on the second insulating layer 830. The first wiring layer 910 and the second wiring layer 920 are electrically connected to each other through via holes 830x which penetrate the second insulating layer 830.
A third insulating layer 840 is formed to cover the second wiring layer 920. A third wiring layer 930 is formed on the third insulating layer 840. The second wiring layer 920 and the third wiring layer 930 are electrically connected to each other through via holes 840x which penetrate the third insulating layer 840.
A solder-resist film 850 which has an opening 850x is formed to cover the third wiring layer 930. The portion of the third wiring layer 930, exposed from the opening 850x of the solder-resist film 850, serves as an electrode pad. In the following, the portion of the third wiring layer 930 exposed from the opening 850x of the solder-resist film 850 will be referred to as an electrode pad 930. Solder bumps 980 are formed on the electrode pads 930. When mounting the semiconductor device 700 on a circuit board (not illustrated), each solder bump 980 serves as an external connection terminal that is electrically connected to a corresponding terminal of the circuit board.
Japanese Laid-Open Patent Publication No. 10-308565 discloses a semiconductor device using a wiring board having a wiring pattern formed on a surface of a core substrate. In this semiconductor device, a semiconductor chip is mounted on the wiring board or built in the wiring board.
However, in the semiconductor device 300 in which the semiconductor chip is mounted on the substrate, there is a problem in that the reliability of the connection at the portions of the solder bumps 410 where the semiconductor chip 400 and the multi-layer substrate 500 are electrically connected is low. Specifically, stress destruction may occur due to the difference in the coefficient of thermal expansion between the semiconductor chip 400 and the multi-layer substrate 500, or disconnection may occur due to electro-migration or the like.
Unlike the semiconductor device 300, the semiconductor device 700 in which the semiconductor chip is built in the substrate does not use the bumps to electrically connect the semiconductor chip 450 and the multi-layer substrate 800, and may have an improved reliability of the connection of the semiconductor chip 450 and the multi-layer substrate 800. However, in the case of the semiconductor device 700, after the semiconductor chip 450 is embedded in the resin 810, the first wiring layer 910 is formed on the surface of the resin 810. The wiring layers which are mutually connected to each other cannot be formed on the top and bottom surfaces of the semiconductor chip 450. Hence, it is difficult to attain high-density fabrication of the semiconductor device 700.